CARY YANG, Santa Clara University
Continuous downward scaling in silicon integrated circuit technology into the sub-20 nm regime has created critical challenges in chip manufacturing, among them, reliability and performance of on-chip interconnects. Current interconnect materials, Cu and W, face increased reliability challenges in the nanoscale as a result of electromigration failures at high current densities. Materials such as nanocarbons, metal silicides, cobalt, ruthenium, and metallic nanowires are being considered as potential replacements for Cu and W. In particular, due to its superior electrical and mechanical properties as well as much higher current-carrying capacities, carbon nanotube (CNT) has been demonstrated to be a serious contender in on-chip interconnect via. However, the main challenge to functionalizing CNT vias is the metal-CNT contact resistance. To mitigate such challenge, a seamless three-dimensional all-carbon interconnect structure is conceived and fabricated by growing CNTs directly on one or few layers of graphene (MLG). This 3D structure can potentially yield low resistance due to the strong C-C sp2 bonding in CNT and graphene and across the CNT-graphene interface. While such growth has been demonstrated, the CNT/graphene interfacial nanostructure and how it impacts the electrical properties of the 3D structure are far from being understood.
Our test structure consists of MLG grown by annealing a Ni thin film in H2/CH4 ambient inside a low-pressure PECVD chamber, before being transferred onto an oxide-covered silicon substrate. Vertically aligned CNTs are then grown on the transferred MLG in a PECVD system using a recipe similar to that in our previous work on CNT vias with chromium underlayer, resulting in a 3D all-carbon interconnect structure. Scanning and transmission electron microscopy images reveal CNT alignment and interfacial nanostructure comparable to the CNT-Cr interface in CNT via. The measured resistance of the 3D structure is compared with those of sub-100 nm linewidth CNT vias. Our results demonstrate the feasibility of fabricating a 3D CNT/graphene device, which can serve as the building block for all-carbon interconnects. Enhanced understanding of the relationship between interfacial nanostructure and device resistance can lead to eventual functionalization of contacts between CNT vias and a graphene-based planar interconnect network in the most advanced technology nodes.
Cary Y. Yang received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Pennsylvania. After working at M.I.T., NASA Ames Research Center, and Stanford University on electronic properties of nanostructure surfaces and interfaces, he founded Surface Analytic Research, a Silicon Valley company focusing on sponsored research projects covering various applications of surfaces and nanostructures. He joined Santa Clara University in 1983 and is currently Professor of Electrical Engineering and Director of TENT Laboratory, a SCU facility located inside NASA Ames. He was the Founding Director of Microelectronics Laboratory and Center for Nanostructures, and served as Chair of Electrical Engineering and Associate Dean of Engineering at Santa Clara. His research spans from silicon-based nanoelectronics to nanostructure interfaces in electronic, biological, and energy-storage systems. An IEEE Life Fellow, he served as Editor of the IEEE Transactions on Electron Devices, President of the IEEE Electron Devices Society, and elected member of the IEEE Board of Directors. He was appointed Vice Chair of the IEEE Awards Board in 2013 and 2014. He received the 2004 IEEE Educational Activities Board Meritorious Achievement Award in Continuing Education “for extensive and innovative contributions to the continuing education of working professionals in the field of micro/nanoelectronics,” and the IEEE Electron Devices Society Distinguished Service Award in 2005. From 2008 to 2013, he held the Bao Yugang Chair Professorship at Zhejiang University in China.
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